A New High-Speed Booth Multiplier Using Modified Components

Abstract

A new multiplier has been presented. Multiplication is a basic and important building block in all arithmetic logic units. Due to
the large delay of multipliers, different methods have been designed to increase speed. In this study, a novel tree multiplier structure
is presented that has regularity of array multipliers and the efficiency of tree multipliers and is capable to implement in large
structures. In partial product generation step a new recoding technique is proposed. This algorithm efficiently decreases number
of partial products. In partial product reduction step, a modified Dadda structure is presented. This method sums partial products
efficiently and is regular. In final addition step a high-speed propagate adder is designed which adds two final operands. Simulations
are done using HSPICE and C codes. Proposed multiplier implementation decreases number of transistor count about 8.5 percent,
delay reduction is 10 percent and power dissipation is decreased 11 percent in compare with other multiplication algorithms.