A New High Speed, Area Efficient 7-2 Compressor for Fast Arithmetic Operations

Abstract

This paper presents a new high speed, low power 7-2 compressor which is constructed according to a sensible combination of pass transistor
logics and static logics. It is constructed of a new 5-4 arithmetic block and two 3-2 counters. The new 5-4 arithmetic block is designed based on a new
truth table. So, a simple 7-2 compressor is designed only with 124 transistors. Therefore, a decrease of gate level delays is achieved which lowers its
power dissipation. Also, the driving problems are decreased, considerably. Furthermore, the decrease of middle stages' capacitances and utilizing
voltage full swing logics have enhanced the speed of cascaded operations. The total latency and power dissipation of the proposed 7-2 compressor are
about 470ps and 670μw, respectively, which is simulated by HSPICE using TSMC 0.18μm CMOS technology