An Ultra Low Power Successive Approximation ADC for Wireless Sensor Network

Abstract

In this paper, a new low-power SARADC is presented. In the presented design, the frequency dependency of the power rather than the
conventional supply voltage is emphasized. Our evaluations show that when the frequency of a mixed signal system drops down, the ratio of
power consumption in analog and digital units have different patterns. In this respect, for our target study of SARADC the power share in
analog is about constant while the share of digital sections is rapidly reduced. This means that to lower the total power, the analog section must
be optimized. In our target study, the SARADC has a major analog unit as a comparator. The frequency of the target design is selected in range
50 KHz - 200 KHz, which is the conventional range of operations for ADC in Wireless Sensor Network (WSN) nodes. The 6bit SARADC
reported here consumes only 4.96 µW at 100 KHz. Ultra low power consumption of our ADC makes this suitable for WSN node applications.
The proposed 6bit SARADC is designed and simulated in 90nm CMOS at 1v supply voltage.