A Power Efficient Register File Architecture in Embedded Processors

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Authors

  • Leila REIKHTECHI
  • Mahdi FAZELI
  • Ahmad PATOOGHY

Keywords:

Embedded Systems, Fault Tolerant, Low Power Design, Register File

Abstract

Reliability and energy efficiency are usually two opposing factors that are both critical in embedded processors. In this paper we
present a register file-partitioningalgorithm, which accounts for both the AVF and access rate. Using this algorithm we divide the
register file into protected and unprotected regions. We show that this algorithm can reduce the AVF by 65% while simultaneously
reducing the energy consumption by 13% on an ARM processor for selected test benches.

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Published

2019-06-04

How to Cite

REIKHTECHI, L., FAZELI, M., & PATOOGHY, A. (2019). A Power Efficient Register File Architecture in Embedded Processors. International Journal of Natural and Engineering Sciences, 7(3), 36–42. Retrieved from https://ijnes.org/index.php/ijnes/article/view/168

Issue

Vol. 7 No. 3 (2013): 2013-3

Section

Articles