REIKHTECHI, L.; FAZELI, M.; PATOOGHY, A. A Power Efficient Register File Architecture in Embedded Processors. International Journal of Natural and Engineering Sciences, [S. l.], v. 7, n. 3, p. 36–42, 2019. Disponível em: https://ijnes.org/index.php/ijnes/article/view/168. Acesso em: 14 nov. 2024.